Silicon Labs /Series0 /EZR32LG /EZR32LG330F128R55 /PCNT2 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)MODE 0 (CNTDIR)CNTDIR 0 (EDGE)EDGE 0 (FILT)FILT 0 (RSTEN)RSTEN 0 (HYST)HYST 0 (S1CDIR)S1CDIR 0 (BOTH)CNTEV 0 (NONE)AUXCNTEV

CNTEV=BOTH, MODE=DISABLE, AUXCNTEV=NONE

Description

Control Register

Fields

MODE

Mode Select

0 (DISABLE): The module is disabled.

1 (OVSSINGLE): Single input LFACLK oversampling mode (available in EM0-EM2).

2 (EXTCLKSINGLE): Externally clocked single input counter mode (available in EM0-EM3).

3 (EXTCLKQUAD): Externally clocked quadrature decoder mode (available in EM0-EM3).

CNTDIR

Non-Quadrature Mode Counter Direction Control

EDGE

Edge Select

FILT

Enable Digital Pulse Width Filter

RSTEN

Enable PCNT Clock Domain Reset

HYST

Enable Hysteresis

S1CDIR

Count direction determined by S1

CNTEV

Controls when the counter counts

0 (BOTH): Counts up on up-count and down on down-count events.

1 (UP): Only counts up on up-count events.

2 (DOWN): Only counts down on down-count events.

3 (NONE): Never counts.

AUXCNTEV

Controls when the auxiliary counter counts

0 (NONE): Never counts.

1 (UP): Counts up on up-count events.

2 (DOWN): Counts up on down-count events.

3 (BOTH): Counts up on both up-count and down-count events.

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